Spring 2026
Hardware Design (6CCE3HAD) - Undergraduate
The module provides a foundational, ISA‑to‑hardware understanding that enables students to design and reason about basic processors, pipelines, and memory systems, and to clearly communicate hardware design decisions.
Staff
Aims
This module introduces hardware design from the Instruction Set Architecture (ISA) upward, connecting the programmer-visible machine model (instructions, registers, and memory abstraction) to the underlying hardware structures (datapath, control, pipelines, caches, and the memory hierarchy). Building on prior knowledge of combinational and sequential logic, you will learn how these components compose into a complete processor–memory system, and how to reason about correctness and performance using simple engineering models.
By the end of the module, you should be able to explain and trace basic processor microarchitectures, analyze pipelined execution, and evaluate memory-system trade-offs in caches and virtual memory.
Learning Outcomes
On successful completion of this module, students will be able to:
ISA and machine-level interface (conceptual)
1.Explain the role of an Instruction Set Architecture (ISA) as a contract between software and hardware. 2.Describe key ISA concepts at a high level (e.g., instruction classes, registers, load/store interface, control flow, memory addressing).
Processor design and control
3.Construct and explain a single-cycle CPU datapath for a small instruction subset (ALU, load/store, branch). 4.Derive the control signals required to execute instructions (e.g., register write, ALU operation select, memory read/write, PC update). 5.Compare single-cycle vs multi-cycle processor organizations and reason about CPI and clock period trade-offs.
Pipelining and performance
6.Explain a classic 5-stage pipeline and identify structural, data, and control hazards. 7.Apply basic hazard mitigation techniques (e.g., forwarding, stalling, basic branch handling) to predict pipeline behavior. 8.Use simple performance models (e.g., CPI, pipeline penalties) to assess design decisions.
Memory hierarchy, virtual memory, and storage
9.Explain locality and analyze cache behavior using tag/index/offset, mapping, and policies. 10.Compute performance metrics such as AMAT and explain the impact of cache design parameters and miss behavior. 11.Describe the purpose and mechanics of virtual memory (paging, TLB, page faults) at a conceptual and practical level. 12.Explain (at a high level) how main memory (DRAM) and storage/I/O fit into the system, including the motivation for concepts like DMA and memory-mapped I/O.
Professional/engineering skills
13.Communicate design reasoning clearly using block diagrams, timing sketches, and quantitative calculations.
Lecture Schedule
| Week | Topic | Slides | Tutorials |
|---|---|---|---|
| Week 1 | von Neumann Model & Instruction Set Architectures | Lecture 1 | Tutorial 1 |
| Week 2 | Instruction Set Architectures II | Lecture 2 | Tutorial 2 |
| Week 3 | ISA, Microarchitecture, and Assembly | Lecture 3 | Tutorial 3 |
| Week 4 | Single-Cycle Microarchitecture: build the whole CPU once | Lecture 4 | Tutorial 4 |
| Week 5 | Multi-Cycle Microarchitecture and Pipelining | Lecture 5 | Tutorial 5 |
| Week 6 | Pipelined Processor Design | Lecture 6 | Tutorial 6 |
| Week 7 | Memory | Lecture 7 | Tutorial 7 |
| Week 8 | Cache | Lecture 8 | Tutorial 8 |
| Week 9 | Cache II and Storage | Lecture 9 | N/A |
FPGA-based Lab
RISKing 16: A 16-bit RISC CPU
Project Author: Zihao Pu
The RISKing16 is a custom 16-bit Reduced Instruction Set Computer (RISC) processor designed specifically for the HAD26 (Hardware Architecture and Design) course at King’s College London. It serves as a pedagogical “playground,” allowing students to transition from theoretical concepts to practical engineering by building a fully functional CPU from the ground up.
Core Design Philosophy
- Unlike complex industry standards like x86 or ARM, RISKing16 focuses on architectural clarity:
- 16-bit Architecture: Features a compact 16-bit datapath and instruction format, optimized for FPGA implementation (like the Basys3 board).
- Load-Store Architecture: Memory is accessed only via explicit LDR and STR instructions, simplifying the internal datapath.
- Full-Stack Development: Students don’t just write Verilog; they develop the entire ecosystem, including the Instruction Set Architecture (ISA) and a custom Assembler.
Modular Learning: The project is structured to master individual components—such as the ALU, Register File, and Control Unit—before integrating them into a multi-cycle or pipelined processor.
| Component | Weight | Details | Supporting Materials |
|---|---|---|---|
| Task 1 | 20% | Building 16-bit ALU and Shifter | Task 1 Slides |
| Task 2 | 20% | Building CPU Datapath | Task 2 Slides |
| Task 3 | 20% | Building CPU FSM | Task 3 Slides |
| Task 4 | 20% | Supporting Memory | Task 4 Slides |
| Task 5 | 20% | Supporting Branching and IO | Task 5 Slides |
| Bonus | 20% | Pipelining | NA |
Practical Skills
To complement the coursework project and facilitate practical FPGA experience, we have developed three introductory lab demonstrations.
| Component | Topic | Slides | Materials | Instructor | Lab Video |
|---|---|---|---|---|---|
| Lab 1 | Getting started with FPGA and VIVADO | Lab 1 | Lab 1 Code | Zihao Pu | Lab 1 |
| Lab 2 | FPGA Debugging: USING VIO AND ILA | Lab 2 | NA | Stefan Johannesson | Lab 2 |
| Lab 3 | Writing FSM using SystemVerilog | Lab 3 | Lab 3 Code | Ali Alsarraf | Lab 3 |
Useful Tools
| Tool | Description | Source |
|---|---|---|
| Verilog Autograder | The online simulation platform for the project | Verilog Autograder |
| openFPGALoader | Download bitstream to FPGA using any platform, including macOS | openFPGALoader-Document |
Prerequisites
- Basic programming experience (Python, Verilog)
- Boolean algebra (covered in LOD Logic Design)
Resources
- Recommended text: Digital Design and Computer Architecture — Harris & Harris
- Lab recordings:
- Tutorial recordings: