/////////////////////////////////////////////////////////////////
// Module Name: shifter
// Description: shifter for RISKing Processor
// Shift Op Design
// 00 - No shift: out = in
// 01 - Logical left shift by 1 (LSL1): out = in << 1
// 10 - Logical right shift by 1 (LSR1): out = in >> 1
// 11 - Arithmetic right shift by 1 (ASR1): out = {in[15], in[15:1]}
/////////////////////////////////////////////////////////////////


module shifter (
  input logic [15:0] in,
  input logic [1:0] shift_op,
  output logic [15:0] out
  );
  
// Note: No clock needed. Shifter is fully combinational
/*********** Fill your code below *****************/







//*********** End of your code *******************/

endmodule

